1. Field of the Invention
The present invention relates to a liquid crystal display device using a horizontal electric field. More particularly, the present invention relates to a horizontal electric field applying type thin film transistor substrate having a simplified process, and a fabricating method thereof.
2. Description of the Related Art
A liquid crystal display device controls the light transmittance of liquid crystal using an electric field, thereby displaying a picture. The liquid crystal display device is divided into two main types: a vertical electric field applying type and a horizontal electric field applying type based upon the direction of an electric field that drives the liquid crystal.
The vertical electric field applying type liquid crystal display device drives a liquid crystal of TN (twisted nematic) mode using a vertical electric field formed between a pixel electrode and a common electrode which are disposed opposite in upper and lower substrates. The vertical electric field applying type liquid crystal display device has an advantage in that its aperture ratio is high, but a disadvantage in that its viewing angle is as narrow as 90°.
The horizontal electric field applying type liquid crystal display device drives a liquid crystal of IPS (in-plane switching) mode using a horizontal electric field which is formed between a pixel electrode and a common electrode disposed in parallel in the lower substrate. The horizontal electric field applying type liquid crystal display device has an advantage in that its viewing angle is as wide as 160°. Hereinafter, the horizontal electric field applying type liquid crystal display device will be described in detail.
The horizontal electric field applying type liquid crystal display device includes a thin film transistor substrate (lower plate) and a color filter substrate (upper plate) which are opposite to each other and bonded together; a spacer maintaining a cell gap between the two substrates; and a liquid crystal filled in the cell gap.
The thin film transistor substrate includes thin film transistors; a plurality of signal wire lines forming a horizontal electric field by pixels; and an alignment film spread thereon for liquid crystal alignment. The color filter substrate includes a color filter for realizing color; a black matrix for preventing light leakage; and an alignment film formed thereon for liquid crystal alignment.
In the liquid crystal display device, the thin film transistor substrate includes a semiconductor process and requires a plurality of mask processes. Thus, its fabricating method is complicated so as to be a major cause of the manufacturing cost increase of the liquid crystal display panel. In order to solve this, the thin film transistor substrate has been developed in a direction of reducing the number of mask processes. This is because one mask process includes many processes like a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photo-resist peeling process, an inspection process and so on. Accordingly, four mask processes have recently been on the rise, wherein the four mask processes are reduced by one mask process from five mask processes which has been a standard mask process of the thin film transistor substrate.
FIG. 1 is a plan view illustrating a horizontal electric field applying type thin film transistor substrate using four mask processes of the related art, and FIG. 2 is a sectional diagram illustrating the thin film transistor substrate shown in FIG. 1, taken along the lines I-I′, II-II′.
The thin film transistor substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 which are formed on a lower substrate 45 to cross each other with a gate insulating film 46 therebetween; a thin film transistor 6 formed at each crossing part; a pixel electrode 14 and a common electrode 18 which are formed to form a horizontal electric field in a pixel area; and a common line 16 connected to the common electrode 18. And, the thin film transistor includes a storage capacitor 20 formed at an overlapping part of the pixel electrode 14 and the common line 16; a gate pad 24 connected to the gate line 2; a data pad 30 connected to the data line 4; and a common pad 36 connected to the common line 16.
The gate line 2 supplying a gate signal and the data line 4 supplying a data signal are formed in a cross structure to define a pixel area.
The common line 16 supplying a reference voltage for driving liquid crystal is formed substantially parallel to the gate line 2 with a pixel area therebetween.
The thin film transistor 6 receives the pixel signal of the data line 4 to be charged and kept in the pixel electrode 14 in response to the gate signal of the gate line 2. The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2; a source electrode 10 connected to the data line 4; a drain electrode 12 connected to the pixel electrode 14; an active layer 48 which overlaps the gate electrode 8 with a gate insulating film 46 therebetween to form a channel between the source electrode 10 and the drain electrode 12; and ah ohmic contact layer 50 for being in ohmic contact with the source and drain electrodes 10, 12 and the active layer 48.
The active layer 48 and the ohmic contact layer 50 are formed to overlap the data line 4, the data pad lower electrode 32, and a storage upper electrode 22.
The pixel electrode 14 is connected to the drain electrode 12 of the thin film transistor 6 through a first contact hole 13 penetrating a passivation film 52. The pixel electrode 14 is connected to the drain electrode 12, and includes a first horizontal part 14A formed parallel to the adjacent gate line 2; a second horizontal part 14B formed to overlap the common line 16; and a finger part 14C formed in perpendicular between the first and second horizontal parts 14A, 14B.
The common electrode 18 is connected to the common line 16 and formed at a pixel area. The common electrode 18 is formed parallel to the finger part 14C of the pixel electrode 14 in the pixel area 5.
Accordingly, a horizontal electric field is formed between the pixel electrode 14 to which a pixel signal is supplied through the thin film transistor 6 and the common electrode 18 to which a reference voltage (hereinafter, referred to as “common voltage”) is supplied through the common line 16. Specifically, the horizontal electric field is formed between the common electrode 18 and the finger part 14C of the pixel electrode 14. The liquid crystal molecules, which are arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate by such a horizontal electric field, rotate by dielectric anisotropy. And, the transmittance of the light transmitted through the pixel area is changed in accordance with the extent of rotation of the liquid crystal molecules, thereby realizing a gray level.
The storage capacitor 20 includes the common line 16 and the storage upper electrode 22 which overlap the common line 16 with the gate insulating film 46, the active layer 48 and the ohmic contact layer 50 and is connected to the pixel electrode 14 through a second contact hole 21 that is formed in the passivation film 50. The storage capacitor 20 is made to stably keep the pixel signal charged in the pixel electrode until the next pixel signal is charged.
The gate line 2 is connected to a gate driver (not shown) through the gate pad 24. The gate pad 24 includes a gate pad lower electrode 26 extended from the gate line 2; and a gate pad upper electrode 28 connected to the gate pad lower electrode 26 through a third contact hole 27 penetrating the gate insulating film 46 and the passivation film 52.
The data line 4 is connected to a data driver (not shown) through the data pad 30. The data pad 30 includes a data pad lower electrode 32 extended from the data line 4; and a data pad upper electrode 34 connected to the data pad lower electrode 32 through a fourth contact hole penetrating the passivation film 52.
The common line 16 receives a common voltage from an external common voltage source (not shown) through the common pad 36. The common pad 36 includes a common pad lower electrode 38 extended from the common line 16; and a common pad upper electrode 40 connected to the common pad lower electrode 38 through a fifth contact hole 39 penetrating the gate insulating film and the passivation film 52.
A fabricating method of the thin film transistor substrate having such a configuration is described in detail by use of four mask processes as shown in FIGS. 3A to 3d. 
Referring to FIG. 3A, a gate metal pattern inclusive of the gate line 2, the gate electrode 8, the gate pad lower electrode 26, the common line 16, the common electrode 18 and the common pad lower electrode 38 is formed on the lower substrate 45 by use of a first mask process.
To describe in detail, a gate metal layer is formed on the lower substrate 45 by a deposition method such as sputtering. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask, thereby forming the gate metal pattern inclusive of the gate line 2, the gate electrode 8, the gate pad lower electrode 26, the common line 16, the common electrode 18 and the common pad lower electrode 38. The gate metal layer is formed of metal of Al, Mo, Cr in a single or double layer structure.
Referring to FIG. 3B, the gate insulating film 46 is spread on the lower substrate 45 where the gate metal pattern is formed. And there are formed a semiconductor pattern inclusive of the active layer 48 and the ohmic contact layer 50; and a source/drain metal pattern inclusive of the data line 4, the source electrode 10, the drain electrode 12; the data pad lower electrode 32 and the storage upper electrode 22.
To describe in detail, the gate insulating film 46, an amorphous silicon layer, n+ amorphous silicon layer and the source/drain metal layer are sequentially formed by a deposition method such as PECVD, sputtering on the lower substrate 45 where the gate metal pattern is formed. Herein, the material of the gate insulating film 46 is mainly an inorganic insulating material such as SiOx, SiNx and so on. The source/drain metal layer is formed of metal of Al, Mo, Cr system in a single or double layer structure. And then, a photo-resist pattern having a stepped difference is formed on the source/drain metal layer by the photolithography process using a second mask. The source/drain metal layer is patterned by use of the photo-resist pattern having the stepped difference, thereby forming the source/drain metal pattern inclusive of the data line 4, the source electrode 10, the drain electrode integrated with the source electrode 10, and the storage upper electrode 22. And, the n+ amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photo-resist pattern, thereby forming the ohmic contact layer 50 and the active layer 48. Subsequently, the source/drain metal pattern exposed by ashing the photo-resist pattern is etched along with the ohmic contact layer 50, thereby separating the source electrode 10 and the drain electrode 12.
And then, the photo-resist pattern remaining on the source/drain metal pattern is removed by a stripping process.
Referring to FIG. 3C, the passivation film 52 inclusive of the first to fifth contact holes 13, 21, 27, 33, 39 is formed by a third mask process on the gate insulating film 46 where the source/drain metal pattern is formed.
To describe in detail, the passivation film 52 is formed by the deposition method such as PECVD on the entire surface of the gate insulating film 46 where the source/drain metal pattern is formed. Subsequently, the passivation film 52 is patterned by the photolithography process and the etching process using a third mask, thereby forming the first to fifth contact holes 13, 21, 27, 33, 39. The first contact hole 13 exposes the drain electrode 12 by penetrating the passivation film 52, and the second contact hole 21 exposes the storage upper electrode 22 by penetrating the passivation film 52. The third contact hole 27 exposes the gate pad lower electrode 26 by penetrating the passivation film 52 and the gate insulating film 46, and the fourth contact hole 33 exposes the data pad lower electrode 32 by penetrating the passivation film 52. The fifth contact hole 39 exposes the common pad lower electrode 38 by penetrating the passivation film 52 and the gate insulating film 46.
Herein, the material of the passivation film 52 is an inorganic insulating material like the gate insulating film 46, or an organic insulating material such as BCB, PFCB or acrylic organic compound with low dielectric constant.
Referring to FIG. 3D, a transparent conductive pattern inclusive of the pixel electrode 14, the gate pad upper electrode 28, the data pad upper electrode 34 and the common pad upper electrode 40 is formed on the passivation film 54 by use of a fourth mask process.
To describe in detail, a transparent conductive film is spread on the passivation film 52. Subsequently, the transparent conductive film is patterned by the photolithography process and the etching process using a fourth mask, thereby forming a transparent conductive pattern inclusive of the pixel electrode 14, the gate pad upper electrode 28, the data pad upper electrode 34 and the common pad upper electrode 40. The pixel electrode 14 is connected to the drain electrode 12 that is exposed through the first contact hole 13, and is connected to the storage upper electrode 22 that is exposed through the second contact hole 21. The gate pad upper electrode 28 is connected to the gate pad lower electrode 26 that is exposed through the third contact hole 27. The data pad upper electrode 34 is connected to the data lower electrode 32 that is exposed through the fourth contact hole 33. The common pad upper electrode 40 is connected to the common pad lower electrode 38 that is exposed through the fifth contact hole 39.
Herein, the material of the transparent conductive film is ITO (indium tin oxide).
In this way, the related art horizontal electric field applying type thin film transistor substrate and the fabricating method thereof reduces the number of processes to four mask processes, thereby reducing the manufacturing cost proportionally thereto.
However, the common electrode 18 formed in the pixel area is formed of an opaque gate metal. Thus, there is a problem in that the aperture ratio is low.
Further, due to the aperture ratio problem, there is a limit in increasing the overlapping area of the storage upper electrode 22 and the common line 16 formed of the opaque metal. Thus, there is a problem in that the capacity of the storage capacitor 20 is low.